Integrated circuit (IC) designs include large numbers of logic gates and synchronous devices connected by interconnects. ICs are designed according to an IC design flow that specifies the steps and order of the steps performed to design an IC. Some of the steps are automated through implementation of electronic design automation (EDA). The computer software programs that run on computers to contribute to the IC design and/or analyze the IC design are referred to as EDA tools.
One type of EDA tool is a static timing analysis (STA) tool that performs a timing analysis that analyzes an IC design to ensure that timing constraints are met. The STA tool identifies timing violations where the timing constraints are not met, and fixes the timing violations by adding various delays, such as in the form of buffers, that affect the timing of signals propagating through the IC.
Computers, through execution of STA tools, are used to perform the timing analysis given the complexity of IC designs. However, because of their complexity, the STA tools may overestimate the number of timing violations in an IC design upon performing a timing analysis, which in turn may cause the STA tool to add more buffers that are needed to adequately fix the timing problems in the design. As a result, the IC design is larger in size (or footprint) than it needs to be. Thus, ways to improve the STA tools to reduce the overestimation of timing violations and the number buffers unnecessarily added to the IC design may be desirable.